This application claims priority to European Application Serial No. 00402331.3, filed Aug. 21, 2000 and to European Application Serial No. 01400686.0, filed Mar. 15, 2001 U.S. patent application Ser. No. 09/932,651 (TI-31366US) is incorporated herein by reference.
This invention generally relates to microprocessors, and more specifically to improvements in cache memory and access circuits, systems, and methods of making.
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A cache architecture is often used to increase the speed of retrieving information from a main memory. A cache memory is a high speed memory that is situated between the processing core of a processing device and the main memory. The main memory is generally much larger than the cache, but also significantly slower. Each time the processing core requests information from the main memory, the cache controller checks the cache memory to determine whether the address being accessed is currently in the cache memory. If so, the information is retrieved from the faster cache memory instead of the slower main memory to service the request. If the information is not in the cache, the main memory is accessed, and the cache memory is updated with the information.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first aspect of the invention, there is provided a digital system having at least one processor, with an associated multi-segment cache memory circuit. Within the cache, a data array is arranged as a plurality of lines each having one or more segments. Each of the segments has a corresponding dirty bit within a set of dirty bits, each dirty bit is operable to indicate if the corresponding segment contains data that is not coherent with a secondary memory and is therefore referred to as xe2x80x9cdirty.xe2x80x9d
Direct memory access (DMA) circuitry is connected to the memory cache and is operable to transfer data from a selectable portion of segments of the cache to a selectable region of a secondary memory in accordance with the selected portion of dirty bits, such that only segments within the selectable portion of segments whose corresponding dirty bit is in a dirty state are transferred.
An embodiment of the invention has a mode circuit, wherein the DMA circuitry is operable to transfer a block of segments from the local memory to the second memory in a manner that only segments within the block marked as dirty are transferred when the mode circuit is in a first state, and wherein the DMA circuitry is operable ignore the plurality of dirty bits such that the entire block is transferred when the mode circuit is in a second state.
An embodiment of the invention has another mode circuit, wherein the DMA circuitry is operable to set the selected portion of dirty bits to a dirty state if the mode circuit is in a first mode and to set the selected portion of dirty bits to a clean state if the mode circuit is in a second mode.
An aspect of the invention is a method of operating a digital system having a processor and a memory cache. The processor executes instructions and causes transaction requests to the cache. Data and/or instructions are loaded into requested locations within the cache in response to the transaction requests. Dirty bits are set to a dirty state in response to transaction by the processor that writes data to the associated locations in the cache memory. A data item is transferred by direct memory access (DMA) from a first location in the cache memory to a selectable location in a secondary memory that does not necessarily correspond directly to the first location only if a corresponding dirty bit is in a dirty state.
In another embodiment, DMA transfers to the cache are qualified by another mode flag. If the mode flag is in a first state, dirty bits are set to a dirty state by a DMA transfer. If the mode flag is in another state, the dirty bits are set to a clean state by a DMA transfer.